1. Field of the Invention
The present invention relates to semiconductor packages and methods for fabricating the same, and, more particularly, to a semiconductor package having conductive pillars and a method of fabricating the same.
2. Description of Related Art
In the current semiconductor package, a plurality of conductive balls (such as solder balls or bumps) are commonly used as conductive elements for forming electrical connection, an encapsulant is used to encapsulate the chip and the conductive balls, and the two terminals of each of the conductive balls are exposed from the upper and lower surfaces of the encapsulant, respectively, and a build-up structure is disposed on the encapsulant and electrically connected to the chip via the conductive balls.
FIGS. 1A-1G are cross-sectional views showing a semiconductor package 1 and a method of fabricating the same.
As shown in FIG. 1A, a first carrier 10 having a first release layer 101 is provided. A chip 11 and a plurality of conductive balls 12 are disposed on the first release layer 101. The chip 11 has a plurality of solder pads 111 and opposing active and passive surfaces 11a and 11b. Each of the conductive balls 12 has a width W1, and opposing first and second terminals 12a and 12b. 
As shown in FIG. 1B, an encapsulant 13 having first and second surfaces 13a and 13b is formed on the first release layer 101, and encapsulates the chip 11 and the conductive balls 12. A portion of each of the conductive balls 12 is removed, and a length L1 of each of the conductive balls 12 is exposed from the second terminals 12b. 
As shown in FIG. 1C, a second carrier 14 is formed on the second surface 13b of the encapsulant 13 of the FIG. 1B, followed by reversing the whole package of FIG. 1B, and then removing the first carrier 10 via the first release layer 101 thereof.
As shown in FIG. 1D, a build-up structure 15 is formed on the active surface 11a of the chip 11 and the first surface 13a of the encapsulant 13. The build-up structure 15 has at least one dielectric layer 151, a plurality of conductive vias 152 formed in the dielectric layer 151, and at least one wiring layer 153 formed on the dielectric layer 151. The wiring layer 153 has a plurality of conductive pads 154.
As shown in FIG. 1E, an insulative protection layer 16 is formed on the build-up structure 15, and a plurality of under bump metallurgies (UBM) 161 are formed on the insulative protection layer 16 and electrically connected with the conductive pads 154.
As shown in FIG. 1F, a third carrier 17 having a second release layer 171 is disposed on the insulative protection layer 16.
As shown in FIG. 1E the whole package of FIG. 1F is inverted, and the second carrier 14, and the third carrier 17 are removed, followed by forming a plurality of solder balls 18 on the under bump metallurgy 161, so as to form the semiconductor package 1.
The drawback of the prior art is that the conductive balls 12 have a large width W1, and cannot be used in the semiconductor package 1 having fine pitches. Besides, a third carrier 17 is required in the method of fabricating the semiconductor package 1, which undesirably results in an increase in cost of the semiconductor package 1. Moreover, the chip 11 may easily suffer from impact or forces exerted from the encapsulant 13 and thus result in a displacement. Thus, there is a critical need for solving the aforementioned drawbacks.